The present invention relates generally to a method and system to connect multiple radio devices to a host with low enough latencies to meet critical timing requirements.
The current industry standard interface for connecting to lower rate radio chipsets (e.g., 802.11a, 802.11b/g, or pre-802.11n) is a PCI (Personal Computer Interface) connection to a MAC (Media Access Control) device. A single 32-bit, 33 MHZ PCI bus, typically used in current systems, cannot sustain sufficient throughput for multiple high data rate radios. In order to use a PCI interface in a multi-radio high performance system, options include multiple parallel PCI busses and/or a wider/faster PCI bus connection, both of which are not desirable in low-power, low-cost, small form factor systems.
Because of PCI bus interface throughput limitations, and a desire for an interconnect requiring less-power and space (e.g., for laptops and mobile applications), the industry standard interface for high-rate radios is evolving towards the PCI Express (PCIe) standard. Unlike PCI, PCI Express is not a multi-drop bus architecture and thus has an independent PCI Express connection for each device. Standard MPU (MicroProcessor Unit) processors with a PCI Express interface provide a limited number of PCI Express connections (typically 1). Thus, in order to interface multiple radios, a PCI Express switch device is used. However, the standard PCI Express switch device is costly, and does not provide for any performance enhancements other than a basic bus multiplexing function.
In order to provide a very high-end feature and performance set, a radio MAC processor would have to access a number of parallel transmit queues with a fast fetch latency. This would enable such features as: a piggyback ACK (acknowledgement) response to a U-ASPD trigger packet; multiple BSSID support including independent QOS (quality of service) queues; enhanced roaming support; and other performance enhancements. Two options to provide the ability to fetch one of many packets with a low latency are, (1) hold packets local at the radio MAC device in internal or external memory, or (2) hold packets in host memory space.
The first option, storing all packets in local MAC memory, requires a very large memory on each radio MAC device. This can be cost prohibitive, particularly with larger packet sizes, such as is supported by the 802.11n protocol.
The second option, storing all packets in host processor memory, is problematic because of contention issues for the host memory, as well as contention for the PCI Express interface to the host processor. Host memory accesses are shared by host CPU code and data fetches for program execution, CPU processing of packet data, wired side Ethernet data flow, data flow to and from other radio devices, as well as any co-processor functions within the host MPU which access packet data via DMA (direct memory access) transfers. In order to support a guaranteed low latency fetch of a packet within host memory (e.g., DRAM), system design parameters would have to be highly optimized. These optimizations include excessively fast/wide memory devices (which are costly and power hungry) not otherwise required, and highly optimized data flow and bus arbitration options which are generally not feasible in standard MPU devices. Although the PCI Express interface supports a high bandwidth, the single PCI Express connection between a PCI switch and a host MPU provides additional latencies due to the need to arbitrate with other radio devices for the single PCI Express port of the MPU.
The difficulty in meeting critical timing requirements of a high-performance system is further compounded by packet encryption, which is typically performed “offline” in the MAC on a per packet basis. Thus, the entire unencrypted packet is first fetched from the host memory (e.g., DRAM) to MAC local memory (e.g., RAM), then transferred via DMA through an encryption engine, preferably a hardware assisted encryption engine. Because the encryption process can't begin until the packet has been fully uploaded from host memory, the encryption process adds linearly to the time required to transmit a given packet. A further limitation of the current, standard radio MAC encryption process is that while basic encryption engine functions are often hardware assisted, mode specific operations involve MAC CPU processing, which further increases the time required to execute the encryption process.
These and other problems of prior art systems are addressed by the present invention as will be described herein.